The present invention relates to the field of semiconductors, and, more particularly, to non-volatile memory semiconductor devices and associated manufacturing methods.
Semiconductor devices in the form of integrated circuits are widely used in most electronic devices. For example, computers, cellular telephones, and other similar devices typically include one or more integrated circuits (ICs). In addition, many typical types of ICs are based upon metal-oxide semiconductor (MOS) technology wherein each transistor includes doped source and drain regions in a semiconductor substrate, with a well or channel region between the drain and source.
Non-volatile memories are semiconductor devices that are used in a variety of products as such memories retain their contents even when power is no longer supplied to the memory. An Electrically Erasable Programmable Read Only Memory (EEPROM) is a type of non-volatile memory that permits the contents to be erased and different data then stored in the memory. A FLASH memory is a type of EEPROM wherein programming or erasing is done in sectors rather than on an individual cell level. A FLASH memory may typically have better read access times than a conventional EEPROM.
A typical EEPROM device includes an array of memory cells, and, each cell, in turn, includes a floating gate and a control gate over the floating gate. The floating gate is positioned over a channel of the transistor that is defined between spaced apart source and drain regions formed in a semiconductor substrate. Intervening insulating layers are between the channel and floating gate, and between the floating gate and control gate. One type of memory cell configuration is the so-called stacked gate arrangement wherein the control gate is directly over the floating gate. A stacked gate structure is disclosed, for example, in U.S. Pat. No. 5,077,691 to Haddad et al., and U.S. Pat. No. 5,598,369 to Chen et al.
Another configuration is the split gate arrangement wherein the control gate extends over the floating gate, but also extends laterally adjacent the floating gate over a portion of the channel of the transistor. For example, U.S. Pat. No. 5,867,425 to Wong discloses a split gate memory cell including a bipolar transistor arranged such that its collector is the biased depletion region under the channel of a sensing transistor.
More specifically, an oxide layer in a non-volatile memory, i.e. the tunnel oxide layer, is a thin insulating layer of silicon oxide formed over the channel region and which separates the channel region from the overlying floating gate. The floating gate may be a metal or doped polysilicon layer, for example. Next, an interpoly dielectric, i.e. a control gate oxide, and a control gate are sequentially stacked above the floating gate.
As device dimensions have been reduced in semiconductor processing, the quality of the oxides has become even more important. A preferred approach to forming the oxides may be by thermal oxidation. The thermally grown oxide provides good electrical performance, provides good mechanical bonding to the underlying polysilicon and or silicon substrate, and helps to block ion implantation and diffusion of dopants into the channel region.
U.S. Pat. No. 5,851,892 to Lojek et al. discloses a method for making an oxide including both pre- and post-oxidation anneal steps. The patent provides that the anneals, the ambients selected, and various cleaning steps help ensure a high quality gate or tunnel oxide. A portion of the oxide layer grown during the high temperature (1000xc2x0 C.) anneal and subsequent cool down is desirably reduced to less than about 20 xc3x85, and its growth is the necessary byproduct of incorporating oxygen into the oxide bulk for the benefit of improving electrical performance. The oxide layer is described as having an overall thickness of 100 xc3x85.
As device dimensions scale down rapidly with the advance of manufacturing technologies, the electric field in the thin oxides continues to increase. Part of the consequence of such increased electric field and the thinning of the oxides is the increased trap generation at the oxide interface or within the thin oxides. The trap generation and the capture of channel electrons by the traps in turn leads to increased low frequency noise and transconductance degradation. Additionally, the edges and corners of the floating gate between the floating gate and the control gate are susceptible to stress-induced inter-poly leakage.
Unfortunately, despite continuing efforts and developments in the area of forming high quality oxides, device performance and longer term reliability is still compromised by conventional tunnel oxides, especially as device dimensions continue to be reduced.
In view of the foregoing background, it is therefore an object of the present invention to provide a memory device including a high quality oxide layer and a method for making the memory device.
This and other objects, features and advantages in accordance with the present invention are provided by a method of making a non-volatile memory including: forming a source region and a drain region in a silicon substrate and defining a channel region therebetween; forming a tunnel oxide layer adjacent the silicon substrate; forming a polysilicon floating gate layer adjacent the tunnel oxide; and forming a control gate oxide layer adjacent the polysilicon floating gate layer. The control gate oxide layer is formed by growing a first oxide portion by upwardly ramping the polysilicon floating gate layer to a first temperature lower than a glass transition temperature, and exposing the polysilicon floating gate layer to an oxidizing ambient at the first temperature and for a first time period, and growing a second oxide portion between the first oxide portion and the polysilicon floating gate layer by exposing the polysilicon floating gate layer to an oxidizing ambient at a second temperature higher than the glass viscoelastic transition temperature for a second time period so that the second oxide portion has a thickness in a range of about 25 to 75% of a total thickness of the control gate oxide layer Also, a control gate layer is formed adjacent the control gate oxide layer.
The step of upwardly ramping may comprise upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping, and the relatively high ramping rate may be greater than about 35xc2x0 C./minute. The step of growing the first oxide portion may further comprise exposing the polysilicon floating gate layer to an oxidizing ambient containing a relatively small amount of oxygen during the upward ramping to reduce any oxide formed during upward ramping, and the relatively small amount of oxygen may be less than about 10% by volume.
Furthermore, the step of upwardly ramping may comprise upwardly ramping at a relatively high rate and in an ambient so that an oxide thickness formed during the upward ramping is in a range of about 5 to 30% of the total thickness of the control gate oxide layer. The total thickness of the control gate oxide layer may be less than about 50 Angstroms. The first temperature may be less than about 900xc2x0 C. and the second temperature may be greater than about 925xc2x0 C. The first temperature may be in a range of about 750xc2x0 C. to 900xc2x0 C. and the second temperature may be in a range of about 925xc2x0 C. to 1100xc2x0 C. Also, the first oxide portion may be nitrided by adding NO, N2O or NH3 into the oxidant.
The growing steps are preferably carried out in a single processing apparatus such as a furnace, a rapid thermal processor, or a fast thermal processor.
Objects, features and advantages in accordance with the present invention are also provided by a non-volatile memory including a plurality of memory cells formed on a silicon layer each comprising a tunnel oxide layer, a polysilicon floating gate layer, and a graded, grown, control gate oxide layer on the polysilicon floating gate layer The control gate oxide layer includes a first portion and a second portion arranged in stacked relation with the second portion being adjacent the polysilicon floating gate layer and defining an interface therewith. The second portion has a thickness in a range of about 25 to 75% of a total thickness of the control gate oxide layer. The polysilicon floating gate layer and the control gate oxide layer are substantially stress-free adjacent the interface. Each memory cell also includes a control gate layer adjacent the control gate oxide layer, and a source region and drain region in the silicon layer and defining a channel region therebetween.
The interface is preferably substantially planar and may have a roughness of less than about 3 Angstroms. The first portion of the control gate oxide layer and the control gate layer define a second interface, wherein the control gate oxide layer and the control gate layer are substantially stress-free adjacent the second interface. Also, the total thickness of the control gate oxide layer may be less than about 50 Angstroms.